This invention relates to a gate turn-off thyristor which can be controlled in turn-off by an integrated MIS transistor.
A gate turn-off thyristor (hereinafter referred to as a GTO) is usually so formed that it is turned off by applying a negative bias to a gate electrode to allow a portion of an anode current to be externally drawn as a gate current. The turn-off operation of such an ordinary GTO is of a current control type, requiring a fairly great gate power. It is known that an MIS transistor by which gate-to-cathode can be shorted in turn-off is monolithically formed within the GTO. This type of the GTO is known, for example, as an MIS controlled GTO. For easiness in explanation, this GTO is hereinafter referred to merely as an MIS GTO. The MIS GTO requires a smaller gate power for turn-off, because its operation is of a voltage-controlled type. There are two types of MIS GTO, one is using an n-channel MIS transistor (for example, Japanese Patent Publication (Kokoku) No. 59-47469) and the other is using a p-channel MIS transistor (for example, Japanese Patent Publication (Kokoku) No. 60-9668). In the n-channel MIS transistor, the surface portion of a p-base layer in the GTO is used as a channel region and an additional n-type layer is formed within the p-base layer such that it acts as one of source and drain regions. And in the p-channel MIS transistor, the surface portion of the periphery of an n-emitter layer in the GTO is used as a channel region and a p-type layer is formed within the n-emitter layer such that it acts as one of the source or drain regions. In the MIS GTO, when the MIS transistor is rendered on, then, a portion of an anode current is bypassed through the MIS transistor. Where the channel conductance of the MIS transistor is greater than a given value, then most of an anode current flows into the cathode electrode through a bypass. As a result, a quantity of electrons injected from the n-emitter layer into the p-base layer is decreased, failing to maintain the GTO in an on-state, so that the GTO is shifted to the off-state.
A maximum anode current level (peak turn-off current level) I.sub.TGQM, at which the MIS GTO can be turned off, depends upon a resistance R.sub.S of the bypass which is formed when the MIS transistor of turned on. The maximum anode current level is given below: EQU I.sub.TGQM =G.sub.OFF .multidot.V.sub.NP /R.sub.S ( 1)
where
V.sub.NP : a voltage drop, in the on-state, of an emitter junction formed between the second base layer and the second emitter layer, as given by about 0.8 V; and PA1 G.sub.OFF : a gate turn-off gain as given by a ratio of the anode current to the gate current at the gate turn-off time. PA1 R.sub.ON : the ON resistance of the MIS transistor; PA1 R.sub.L : the lateral resistance of the second base layer under the second emitter layer; and PA1 R.sub.V : the vertical resistance of said second base layer.
The resistance R.sub.S is expressed as follows: EQU R.sub.S =R.sub.ON +R.sub.L +R.sub.V ( 2)
where
As evident from the above, it is important to reduce the resistance R.sub.S so as to make the peak turn-off current I.sub.TGQM of the MIS GTO larger. In order to make the ON resistance R.sub.ON of the MIS transistor smaller it is desirable that the channel length of the MIS transistor be made as small as possible and that the channel width of the MIS transistor be made as great as possible. In order to make the resistances R.sub.L and R.sub.V of the second base layer smaller, it is desirable that the whole length of the aforementioned bypass be shortened through the microminiaturization of respective regions of the element and that the impurity concentration level of the second base layer be made higher. Of these requirements, the shape and dimension requirement can readily be met by a recently developed microminiaturization technique. It is, however, difficult to increase the impurity concentration level of the second base layer in view of its relation to the element characteristics. That is, the MIS GTO requires an emhancement type MIS transistor of a proper threshold voltage. It is, therefore, necessary that the impurity concentration level of the second base layer which is used as a channel region of the MIS transistor be maintained at a level lower than about 10.sup.17 /cm.sup.3. Therefore, the conventional method has been directed to reducing the dimension of the second emitter layer through a division and hence to reducing the resistance R.sub.L. This results in a decrease in the effective area of the GTO element region in the MIS GTO element, an increase in the on-state voltage of the MIS GTO and a decrease in the surge current capability.